Phase locked loops (PLLs) are used in a wide variety of electronic devices. In operation, a PLL generates an output clock signal that is locked in phase (i.e. synchronous) with a reference clock. If the PLL loses the reference clock, the PLL's output clock signal, which tracks the reference clock, may be reduced to zero (0) Hertz (Hz), or another low frequency. For many applications, it is desirable for the PLL to produce a stable output clock signal, even during a loss of the reference clock signal. Thus, there is a continued need to improve the stability of a PLL output clock signal during an unexpected loss of a reference clock signal.